2.20.2007
Trevor Blackwell's walking robot
2.17.2007
Robot-driven cars on roads by 2030
Robot-driven cars on roads by 2030
From the article:
From the article:
- The first wave of intelligent robot cars, capable of understanding and reacting to the world around them, will be tested this November in a competition run by the US Defense Advanced Research Projects Agency (DARPA)...
Thrun, who was speaking at the American Association for the Advancement of Science annual meeting in San Francisco, is a member of the Stanford team participating in the DARPA competition, which will take place on November 3.
Stanford's entrant "Junior" is a converted 2006 Volkswagen Passat whose steering, throttle and brakes all have been modified by engineers to be completely computer-controllable.
An array of lasers fitted on the car bumpers, radar and global positioning systems feed data into the on-board computer to determine its location and position.
Thrun predicted that leaps in artificial intelligence would lead to driverless cars on the roads by 2030.
"Today we can drive about 100 miles (160 kilometers) before human assistance is necessary, by 2010 I expect this to go 1,000 miles (1,160 kilometers), by 2020 up to a million miles (1.6 million kilometers)," he said."
- "I think they'll be on the battlefield by around 2015," he said. "It is going to make sense to use them in situations such as convoys, or in hostile environments where there is danger to personnel."
2.14.2007
Intel's Tera-scale initiative
Intel has announced its path toward tera-scale computing, allowing "Teraflops of performance operating on Terabytes of data." The centerpiece of the progra right now is an 80-core demo chip with a radical architecture. Here is a great article with lots of graphics describing Intel's approach:
The Era of Tera: Intel Reveals more about 80-core CPU
Here is a shorter version: Intel pieces together 80-core processor
Power consumption for the chip is in the 60-watt range.
"The first teraflop chips are expected to reach manufacturing stage by 2010 to 2015."
As Moore's law continues, that means that we start seeing Petaflop chips in the 2030 to 2035 range, and at that point we have the processing power of the human brain on a single chip. See Robotic Nation for the implications of such a chip.
The Era of Tera: Intel Reveals more about 80-core CPU
Here is a shorter version: Intel pieces together 80-core processor
Power consumption for the chip is in the 60-watt range.
"The first teraflop chips are expected to reach manufacturing stage by 2010 to 2015."
As Moore's law continues, that means that we start seeing Petaflop chips in the 2030 to 2035 range, and at that point we have the processing power of the human brain on a single chip. See Robotic Nation for the implications of such a chip.
IBM speeds chips with DRAM memory
IBM speeds chips with DRAM memory: "In an upgrade that could improve chip performance for gamers and multimedia users, IBM plans to double the performance of its microprocessors in 2008 by using smaller, more efficient memory, according to a paper presented at the ISSCC (International Solid State Circuits Conference) trade show in San Francisco Wednesday.
IBM plans to use dynamic RAM (DRAM) instead of static RAM (SRAM) as the embedded memory cache built onto each chip. The change will allow each chip to store its data in one-third the area and use one-fifth the electricity for standby power, said Subramanian Iyer, director of 45-nanometer technology development at IBM.
The approach will vastly improve chip performance for multicore processors and for applications that need to move large amounts of graphic data, such as gaming, networking and image-intensive multimedia, he said. IBM is already using the new embedded DRAM (eDRAM) in 65nm prototype chips, and plans to roll it out commercially by 2008 for its entire range of 45nm chips, including its Power line."
"Doubling performance" is a good thing.
Archives
IBM plans to use dynamic RAM (DRAM) instead of static RAM (SRAM) as the embedded memory cache built onto each chip. The change will allow each chip to store its data in one-third the area and use one-fifth the electricity for standby power, said Subramanian Iyer, director of 45-nanometer technology development at IBM.
The approach will vastly improve chip performance for multicore processors and for applications that need to move large amounts of graphic data, such as gaming, networking and image-intensive multimedia, he said. IBM is already using the new embedded DRAM (eDRAM) in 65nm prototype chips, and plans to roll it out commercially by 2008 for its entire range of 45nm chips, including its Power line."
"Doubling performance" is a good thing.
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